A high-performance Decision Feedback Equalizer (DFE) in a receiver employs high precision sample latches to capture and quantize an incoming high-speed signal. DFE performance depends on the sample latch accuracy, for example, the sample latch voltage offset. To mitigate DFE performance degradation, sample latch voltage offset must be calibrated. However, voltage offset calibration in conventional designs are limited by the precision of relative geometric dimensions of the underlying transistors. As a result, voltage offset calibration may have a restricted offset calibration range if the offset calibration step size is too small, or voltage offset calibration may have poor calibration precision if the offset calibration step size is too large. That is, the precision of relative transistor dimensions affects voltage offset calibration accuracy. And, in turn, the voltage offset calibration accuracy affects DFE performance.